Parallel processors are used to achieve greater reliability in a synchronous data system. For instance, two central processors are operated in parallel in a telecommunications system, to obtain redundancy. One of the central processors has control over the surroundings, whereas the other central processor is inactive and functions solely to take over control should errors occur in the first processor or said processor should malfunction. Both processors operate synchronously. The status of the two processors is constantly identical during execution, provided that no error or fault exists. In order to discover the existence of a possible error or fault, each processor generates after each instruction cycle a data word that shows the internal status of the processor. The status words include bits that represent different units in respective processors. For instance, a main memory unit may be represented by one or more of the bits in the status word. An error in one of the processors is discovered by comparing the status words of respective processors with one another, after each clock cycle. In this respect, the status word generated by the first central processor is sent to the second central processor for comparison. The transmitted status word is compared in the second central processor with a corresponding status word that has been generated in a corresponding clock cycle in the second central processor. The two status words will be identical in the absence of any error or malfunctioning unit in the processors. On the other hand, the status words will differ in the event of an error or malfunctioning unit in the processors, and an analysis is made to establish which of the processors has the fault or is in error.
European Patent Application EP 00752656 A teaches an error tolerant system that includes two central processors which execute instructions in parallel and thus perform the same operations at the same points in time. A copy of each instruction from each processor is received by a control element and compared continuously.
A problem occurs with expanded processor complexity. Greater processor complexity means that more processor units must be supervised, which, in turn, means that the transmitted status words must include more bits. Moreover, status words are generated at a much higher rate in keeping with the higher execution speeds of these expanded processors. This greater complexity and higher execution speed together mean that the system requires a higher bandwidth for the transmission of status words between two parallel processors.